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Quadrature counter
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:51:28 01/06/2011
-- Design Name:
-- Module Name: quadrature_counter - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: debouncer
--
-- Revision: 1.3
-- Additional Comments:
-- TODO: - add a load value
-- - add a custom inc/dec value
-- - include bcd counter?
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity quadrature_counter is
generic (
NB_BITS : positive; -- nb bits of the counter
COUNTER_RESET : integer range 0 to 2**NB_BITS-1; -- counter reset value
COUNTER_MIN : integer range 0 to 2**NB_BITS-1; -- counter min value
COUNTER_MAX : integer range 0 to 2**NB_BITS-1 -- counter max value
);
port (
clk, reset : in std_logic;
enable : in std_logic; -- counter enable
a : in std_logic; -- quadrature channel A
b : in std_logic; -- quadrature channel B
reverse : in std_logic; -- reverse quadrature direction
up : in std_logic; -- up signal
down : in std_logic; -- down signal
counter : out std_logic_vector(NB_BITS-1 downto 0); -- counter
no_cycle : in std_logic -- prevent counter to cycle at min/max
);
end entity quadrature_counter;
architecture RTL of quadrature_counter is
signal a_prev : std_logic; -- previous value of channel A
signal a_pulse : std_logic; -- channel A pulse detection
signal value : integer range 0 to 2**NB_BITS-1; -- internal working value of the counter
signal quadrature_up, quadrature_down : std_logic; -- generated by quadrature
signal up_prev : std_logic; -- previous value up signal
signal up_pulse : std_logic; -- up signal pulse detection
signal down_prev : std_logic; -- previous value down signal
signal down_pulse : std_logic; -- down signal pulse detection
signal counter_up, counter_down : std_logic; -- resulting signals
begin
-- Assignations
quadrature_up <= (b xor reverse) when a_pulse = '1' else '0';
quadrature_down <= not (b xor reverse) when a_pulse = '1' else '0';
counter_up <= quadrature_up or up_pulse;
counter_down <= quadrature_down or down_pulse;
counter <= conv_std_logic_vector(value, NB_BITS);
-- Processes
-- Quadrature channel A pulse generator
quadrature_pulse_gen: process (clk, reset)
begin
if reset = '1' then
a_prev <= '1';
a_pulse <= '0';
elsif rising_edge(clk) then
if a = '1' and a_prev = '0' then
a_pulse <= '1';
else
a_pulse <= '0';
end if;
-- Update previous channel A value
a_prev <= a;
end if;
end process quadrature_pulse_gen;
-- Up pulse generator
up_pulse_gen: process (clk, reset)
begin
if reset = '1' then
up_prev <= '1';
up_pulse <= '0';
elsif rising_edge(clk) then
if up = '1' and up_prev = '0' then
up_pulse <= '1';
else
up_pulse <= '0';
end if;
-- Update previous up value
up_prev <= up;
end if;
end process up_pulse_gen;
-- Down pulse generator
down_pulse_gen: process (clk, reset)
begin
if reset = '1' then
down_prev <= '1';
down_pulse <= '0';
elsif rising_edge(clk) then
if down = '1' and down_prev = '0' then
down_pulse <= '1';
else
down_pulse <= '0';
end if;
-- Update previous up value
down_prev <= down;
end if;
end process down_pulse_gen;
-- Counter update
counter_update: process(clk, reset)
begin
if reset = '1' then
value <= COUNTER_RESET; -- load reset value
elsif rising_edge(clk) and enable = '1' then
-- Up
if counter_up = '1' then
if no_cycle = '0' then
if value = COUNTER_MAX then
value <= COUNTER_MIN;
else
value <= value + 1;
end if;
elsif value /= COUNTER_MAX then
value <= value + 1;
end if;
-- Down
elsif counter_down = '1' then
if no_cycle = '0' then
if value = COUNTER_MIN then
value <= COUNTER_MAX;
else
value <= value - 1;
end if;
elsif value /= COUNTER_MIN then
value <= value - 1;
end if;
end if;
end if;
end process counter_update;
end architecture RTL;Binary to BCD converter
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:13:07 01/07/2011
-- Design Name:
-- Module Name: bin2bcd - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bin2bcd is -- rename to bin2bcd
generic (
NB_BITS : positive; -- nb bits of data in
NB_DIGITS : positive -- nb digits outs
);
port (
binary_in : in std_logic_vector(NB_BITS-1 downto 0); -- binary data in
bcd_out : buffer std_logic_vector(NB_DIGITS*4-1 downto 0) -- bcd data out (digits)
);
end entity bin2bcd;
architecture RTL of bin2bcd is
begin
main: process(binary_in)
variable temp : std_logic_vector(NB_BITS+NB_DIGITS*4-1 downto 0); -- contains digits out and data in
begin
temp := (others => '0'); -- reset internal var
temp(NB_BITS-1+3 downto 3) := binary_in; -- initial 3 bits left shifting
for j in 1 to NB_BITS-3 loop -- shift left remaining bits
for i in 1 to NB_DIGITS-1 loop
if temp(NB_BITS+4*i-1 downto NB_BITS+4*(i-1)) > 4 then
temp(NB_BITS+4*i-1 downto NB_BITS+4*(i-1)) := temp(NB_BITS+4*i-1 downto NB_BITS+4*(i-1)) + 3;
end if;
end loop;
temp(NB_BITS+NB_DIGITS*4-1 downto 1) := temp(NB_BITS+NB_DIGITS*4-2 downto 0); -- shift 1 bit left
end loop;
bcd_out <= temp(NB_DIGITS*4-1+NB_BITS downto NB_BITS); -- update digits out
end process main;
end architecture RTL;Delta Sigma DAC
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:14 01/26/2011
-- Design Name:
-- Module Name: deltasigma - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity deltasigma is
generic(
NB_BITS : natural := 8
);
port(
clk : in std_logic;
reset : in std_logic;
dacin : in std_logic_vector(NB_BITS-1 downto 0);
dacout : out std_logic
);
end deltasigma;
architecture Behavioral of deltasigma is
signal delta, sigma, latch : std_logic_vector(NB_BITS+1 downto 0);
signal l9 : std_logic;
begin
l9 <= latch(9);
delta <= l9 & l9 & dacin;
sigma <= std_logic_vector(unsigned(delta) + unsigned(latch));
sigmalatch : process (clk,reset)
begin
if reset='1' then
latch <= (others => '0');
elsif rising_edge(clk) then
latch <= sigma;
end if;
end process sigmalatch;
dacout0 : process (clk,reset)
begin
if reset='1' then
dacout <= '0';
elsif rising_edge(clk) then
dacout <= l9;
end if;
end process dacout0;
end Behavioral;PWM DAC
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:14:32 01/30/2011
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwm is
generic(
NB_BITS : integer := 8
);
Port (
input : in STD_LOGIC_VECTOR (NB_BITS-1 downto 0);
output : out STD_LOGIC;
clk : in STD_LOGIC
);
end pwm;
architecture Behavioral of pwm is
signal acc : std_logic_vector(NB_BITS downto 0) := (others => '0');
begin
process(clk,input)
begin
if rising_edge(clk) then
acc <= ('0' & acc(NB_BITS-1 downto 0)) + ('0' & input);
end if;
end process;
output <= acc(NB_BITS);
end Behavioral;GadgetFactory Papilio Buttons/LEDs Wing
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:23:33 02/02/2011
-- Design Name:
-- Module Name: wingbutled - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity wingbutled is
Port (
io : inout STD_LOGIC_VECTOR (7 downto 0);
buttons : out STD_LOGIC_VECTOR (3 downto 0);
leds : in STD_LOGIC_VECTOR (3 downto 0)
);
end wingbutled;
architecture Behavioral of wingbutled is
begin
io(0) <= leds(3);
io(2) <= leds(2);
io(4) <= leds(1);
io(6) <= leds(0);
io(1) <= 'Z';
io(3) <= 'Z';
io(5) <= 'Z';
io(7) <= 'Z';
buttons(3) <= io(1);
buttons(2) <= io(3);
buttons(1) <= io(5);
buttons(0) <= io(7);
end Behavioral;