SDCard controller

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This page explain how the SDCard controller work in this Midi_SynthFpga

SDCard on the desk

The code is suject to change. So this note refer exactly to this code : commit 2f7b3a9e28ed4c27c67b58ab7a6ef23697a34b03.

SDFeed module (inside SD_ss.v)

Pin name Description comments
clk96m in clk96m : freq 96Mhz Max. SD card throughput is freq/2 in bit/s. SD card in SPI should support 50Mbits/s max
rst in Reset Synchronous. Actif at 1
Sclk,mosi,miso,cs SPI
note_on in Start fetch data sequence of data pointed by id value
note off in Stop on-going fetch sequence. Fifo is not cleared.
rd_en in Pulse to request new data on data_out
fifo_full,fifo_halffull,fifo_empty out Fifo status
SDdriver_stat out Driver status:

`define IDLE 3'b000
`define BOOT 3'b001
`define FIRST_FETCH 3'b100
`define FETCH 3'b010
`define WAIT 3'b011

Description of SDdriver

When reset return down. The controller automatically send command to boot the SD card. Then the SD card will be ready to answers to controller request. The controller stay in IDLE state. Today there sis no efficient way to know when the SD card start up sequence is completed.
The relying idea this task, is to automatically at design reset send start-up procedure. It will be completed far before the first note_on pulse come.

When a note_on pulse is provide. The controller go in to state BOOT. In this state. Data are fetch in SD card at offset 0x0 in order to read the partition table and collect information about entry id.
Then the status pass to FIRST_FETCH. This state is particular to the first read. It read data from a given offset until it reach the first 512 byte aligned address. This way it read a maximum of 512 byte. This is the default block size in SD Card setting. Th reading command responding to CMD17 “single read block” will return 512 bytes each time a command is issued.

The system works with a fifo that serve as buffer between an high speed SD card interface : up to 48Mbit/s and read interface 768Kbit/s (48Khz, 2 Byte). This fifo is shape to 256 elements of 2 bytes. When the first transaction is over, the controller go into WAIT state.
Once the fifo have at least 128 elements free, the controller return in FETCH state. A CMD17 command is issue to the SDCard, but this time the controller only send 256 Bytes to the fifo. This mean that for a given buffer to fetch relying on several block, most of the block will be read twice. This is an design choice to keep a fifo instance in line with a DRAM resource in the spartan3e.

Then the controller status will swing between WAIT and FETCH until the all buffer have been fetch.

The controller expect to find a partition table at offset 0x0. The 8 first byte are ignored. Each entry is 8 bytes. The 4 first represent the absolut offset on the SDCard.The 4 second represent the length of the buffer in Byte. Those figure are LSB first. (LSB at lower offset). The maximal number of entries is 63 (512/ 8 -1)

Example of partition table

$xxd -l 64 card_v3.bin
0000000: 0000 0000 0000 0000 8800 0000 125e 0000  .............^..
0000010: 9a5e 0000 3a4b 0000 d4a9 0000 8270 0000  .^..:K.......p..
0000020: 561a 0100 c45d 0000 1a78 0100 12aa 0000  V....]...x......
0000030: 2c22 0200 8270 0000 ae92 0200 74e9 0100  ,"...p......t...

First sample at offset 0x88 and length is 0x5E12 bytes
Second sample offset 0x5E9A and length is 0X4B3A bytes

Description of Sdctrl

This module is responsible to send command to the SDCard in SPI. 3 commands are implemented: CMD0: software reset CMD1: Initiate initialization process CMD17: Read a single block

Description of SDBoot

This module take in charge the start-up process. It drive the CS pin but also the SPI clock that required a low frequency in the early step. It drive spi_cmd module to send CMD0 and CMD1 command to the SDCard

Description of spi_cmd

This module is responsible to send reconized command (CMD0,CMD1 and CMD17) to the SDCard. By the way it serialize data to send and de-serialize received data.


  • Handle up to 4 Drivers and fifo, in order to fetch up to 4 samples concurrently. This way we can play up to 4 samples in the same time. An arbiter will be required to share the SDCard access.
A single Block read at 48Mbit/s is about 85,33us to complete plus overhead. It mean a single sample is provide in about 1,5us. While at 48Khz we read sample every 20,833 us. The ratio between what can provide the SDCard, and what consume the sound mixer at 48Khz is about 13,888. With 4 concurrence channel this ratio is 3,4. Without overhead of lost cycle. We could expect up to 13 concurrent channel. But as the overhead is not correctly known and subject to change each time the design change, it is not very recommended to have to many concurrent channel.
  • Support more than 63 entries in the partition table. Midi Level 2 specifications map up to 60 drum instrument. This lead to very few entry for custom waveform or several set of drum instrument. 2 options are foreseen:
    • support of CMD18 and CMD12 to allow multiple read commands
    • Support of 127 partitions, with a second CMD17 command when it's requiered.